CounterDisplay

Source: Lab4/CounterDisplay.sv (modified 2025-11-10 05:13)

// ============================================================
//  CounterDisplay.sv — Single-file implementation for Lab 4
//  Contains: RegisterFourBit, Counter, SevenSegmentDecode,
//            CounterDisplay (top level)
// ============================================================
`timescale 1ns/1ps

// ------------------------------------------------------------
// 1. RegisterFourBit — synchronous clear, rising-edge load
// ------------------------------------------------------------
module RegisterFourBit(
    input  logic        clock,
    input  logic        clear_n,      // active-low sync clear
    input  logic [3:0]  d,
    output logic [3:0]  q
);
    always_ff @(posedge clock) begin
        if (!clear_n)
            q <= 4'b0000;
        else
            q <= d;
    end
endmodule



// ------------------------------------------------------------
// 2. Counter — wraps mod 16, uses RegisterFourBit
// ------------------------------------------------------------
module Counter(
    input  logic        clock,
    input  logic        clear_n,      // active-low
    input  logic [3:0]  addBy,        // increment amount
    output logic [3:0]  count         // stored result
);
    logic [3:0] count_next;

    // adder (mod 16 wrap occurs naturally)
    assign count_next = count + addBy;

    // register storage
    RegisterFourBit u_reg (
        .clock   (clock),
        .clear_n (clear_n),
        .d       (count_next),
        .q       (count)
    );
endmodule



// ------------------------------------------------------------
// 3. SevenSegmentDecode — same behavior as Lab 3B
//    segments[6:0] = {g,f,e,d,c,b,a}
//    Active-low outputs for DE10-Lite HEX display
// ------------------------------------------------------------
module SevenSegmentDecode(
    input  logic [3:0] digit,
    output logic [6:0] segments   // active LOW
);
    always_comb begin
        // default off (all segments off = all HIGH)
        segments = 7'b111_1111;

        case (digit)
            4'h0: segments = 7'b1000000;
            4'h1: segments = 7'b1111001;
            4'h2: segments = 7'b0100100;
            4'h3: segments = 7'b0110000;
            4'h4: segments = 7'b0011001;
            4'h5: segments = 7'b0010010;
            4'h6: segments = 7'b0000010;
            4'h7: segments = 7'b1111000;
            4'h8: segments = 7'b0000000;
            4'h9: segments = 7'b0010000;
            4'hA: segments = 7'b0001000;
            4'hB: segments = 7'b0000011;
            4'hC: segments = 7'b1000110;
            4'hD: segments = 7'b0100001;
            4'hE: segments = 7'b0000110;
            4'hF: segments = 7'b0001110;
            default: segments = 7'b1111111;
        endcase
    end
endmodule



// ------------------------------------------------------------
// 4. CounterDisplay — TOP LEVEL (set this as top in Quartus)
//    Connects Counter + SevenSegmentDecode
// ------------------------------------------------------------
module CounterDisplay(
    input  logic        clock,       // push button
    input  logic        clear_n,     // push button
    input  logic [3:0]  addBy,       // switches
    output logic [6:0]  Seg0         // HEX0
);
    logic [3:0] count_val;

    // Counter instance
    Counter u_counter (
        .clock   (clock),
        .clear_n (clear_n),
        .addBy   (addBy),
        .count   (count_val)
    );

    // 7-seg display
    SevenSegmentDecode u_seg (
        .digit    (count_val),
        .segments (Seg0)
    );
endmodule

// ============================================================
//  END OF FILE
// ============================================================